1. Technical Field
The present disclosure relates to an interconnect structure and the method for preparing the same. More particularly, the invention is related to an interconnect structure and the method for preparing the same with high process margins.
2. Description of Related Arts
It is a common requirement for Cu-based back-end-of-line (BEOL) stacks to make electrical connections with high aspect ratio tungsten contacts in front-end-of-line (FEOL) processes. As semiconductor devices are made, the interconnection electrically links the devices and conductive line parts together. There are via parts and line parts that form an interconnected structure. The via parts are usually filled with tungsten and the method of deposition is highly developed. The line parts are usually filled with copper, which has high conductivity, low resistance, and is able to prevent electron migration. As devices continue to minimize, the formation of the deep tungsten contacts becomes more and more difficult because of poor etch profiles and a high risk of under etching. Moreover, the alignment margin between the tight pitched copper line and the tungsten via continues to get smaller, and thus causes a higher risk of short-circuiting.
When comparing the present invention to a conventional dual damascene, the present invention has several advantages. In general, the conventional dual damascene requires two steps of dielectric etching: one is for via parts and the other is for trench parts. The conventional dual damascene also derives two pattern processes and two alignment processes. Since the conventional dual damascene comprises such parts and processes, the alignment of the via parts and line parts becomes increasingly difficult due to the minimization of devices. One of the advantages of the present invention is that it requires one less critical alignment step than the conventional dual damascene since a plurality of via holes are self-aligned to a plurality of trenches, which serves as a conducting wire and effectively reduces the risk of short-circuiting and increases the process margin, as shown in FIG. 4. Another advantage of the present invention is that it only requires one dielectric etching process to form the plurality of trenches and the plurality of via holes as opposed to the conventional dual damascene, which requires two dielectric etching processes for the via and the trenches. Another advantage of the present invention is that it does not require WCMP, while the conventional dual damascene needs twice the amount of CMPs for the via and the trenches. In FIGS. 5 and 6, an etching back process for removing a first conductive material on an upper surface of a second insulating layer is performed rather than a tungsten CMP (WCMP) process, which has a high cost and brings about dishing and erosion. Additionally, the line height of the conventional dual damascene is not easy to control in the two dielectric etching processes. The present invention alleviates this issue by allowing line height control with an etch stop layer. The height of the plurality of via holes is defined by the height from a mask layer to the top of the substrate.
In comparison with an all-copper dual damascene, there are a few advantages when utilizing the present invention. The all-copper dual damascene includes via parts and line parts, and both are filled with copper. It can become very challenging for conventional Cu-based processing since a PVD barrier and seed layers are typically needed, which may not have sufficient step coverage inside deep, high aspect ratio vias and also suffers from a phenomenon called “bread loafing” near the opening of the trench, thus leading to copper void formation. The present invention resolves this challenge for copper deposition by filling the plurality of via holes with tungsten and applying a first mask layer, thereby reducing the aspect ratio of the copper metallization that needs to be filled. Due to high aspect ratio holes, the contact structures below the copper interconnects may develop keyholes, which are common in deep contacts. When copper interconnects are directly formed on top of deep contacts with keyholes, copper atoms may penetrate through the contacts and degrade the device performance or suffer from reliability loss. The present invention resolves this issue since it has more reliable tungsten via part separating the copper interconnects from the deep contacts in the substrate that are prone to keyhole formation.